Test generation for SI asynchronous circuits with undetectable faults fromsignal transition graph specification

Citation
E. Oh et al., Test generation for SI asynchronous circuits with undetectable faults fromsignal transition graph specification, IEICE T FUN, E84A(6), 2001, pp. 1506-1514
Citations number
24
Language
INGLESE
art.tipo
Article
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES
ISSN journal
0916-8508 → ACNP
Volume
E84A
Issue
6
Year of publication
2001
Pages
1506 - 1514
Database
ISI
SICI code
0916-8508(200106)E84A:6<1506:TGFSAC>2.0.ZU;2-T
Abstract
In this paper, we propose an approach to test pattern generation for Speed- Independent (SI) asynchronous control circuits. Test patterns are generated based on a specified sequence, which is derived from the specification of a target circuit in the form of a Signal Transition Graph (STG). Since the sequence represents the behavior of a circuit only with stable states, the state space of the circuit can be represented as reduced one. A product mac hine, which consists of a fault-free circuit and a faulty circuit, is const ructed and then the specified sequence is applied sequentially to the produ ct machine. A fault is detected when the product machine produces inconsist ency, i.e., output values of a fault-free circuit and a faulty circuit are different, and the sequentially applied part of the sequence becomes a test pattern to detect the fault. We also propose a test generation method usin g an undetectable fault identification as well as the specified sequence. S ince the reduced state space is a subset of that of a gate level implementa tion, test patterns based on a specification cannot detect some faults. The proposed method identifies those faults with a circuit topology in advance . BDD is used to implement the proposed methods efficiently, since the prop osed methods have a lot of state sets and set operations. Experimental resu lts show that the test generation using a specification achieves high fault coverage over single stuck-at fault model for several synthesized SI circu its. The proposed test generation using a circuit topology as well as a spe cification decreases execution time for test generation with negligible cos t retaining high fault coverage.