Reducing cache energy dissipation by using dual voltage supply

Citation
Vg. Moshnyaga et H. Tsuji, Reducing cache energy dissipation by using dual voltage supply, IEICE T FUN, E84A(11), 2001, pp. 2762-2768
Citations number
19
Language
INGLESE
art.tipo
Article
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES
ISSN journal
0916-8508 → ACNP
Volume
E84A
Issue
11
Year of publication
2001
Pages
2762 - 2768
Database
ISI
SICI code
0916-8508(200111)E84A:11<2762:RCEDBU>2.0.ZU;2-F
Abstract
Due to a large capacitance and enormous access rate, caches dissipate about a third of the total energy consumed by today's processors. In this paper we present a new architectural technique to reduce energy consumption in ca ches. Unlike previous approaches, which have focused on lowering cache capa citance and the number of accesses, our method exploits a new freedom in ca che design, namely the voltage per access. Since in modern block-buffered c aches, the loading capacitance operated on block-hit is much less than the capacitance operated on miss, the given clock cycle time is inefficiently u tilized during the hit. We propose to trade-off this unused time with the s upply voltage, lowering the voltage level on the hit and increasing it on t he miss. Experiments show that the approach can half the cache energy dissi pation without large performance and area overhead.