System-MSPA design of H.263+video encoder/decoder LSI for videotelephony applications

Citation
C. Honsawek et al., System-MSPA design of H.263+video encoder/decoder LSI for videotelephony applications, IEICE T FUN, E84A(11), 2001, pp. 2614-2622
Citations number
11
Language
INGLESE
art.tipo
Article
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES
ISSN journal
0916-8508 → ACNP
Volume
E84A
Issue
11
Year of publication
2001
Pages
2614 - 2622
Database
ISI
SICI code
0916-8508(200111)E84A:11<2614:SDOHEL>2.0.ZU;2-R
Abstract
In this paper, a LSI design for video encoder and decoder for H.263+ video compression is presented. LSI operates under clock frequency of 27 MHz to c ompress QCIF (176 x 144 pixels) at the frame rate of 30 frame per second. T he core size is 4.6 x 4.6 mm(2) in a 0.35 mum process. The architecture is based on bus connected heterogeneous dedicated modules, named as System-MSP A architecture. It employs the fast and small-chip-area dedicated modules i n lower level and controls them by employing the slow and flexible programm able device and an external DRAM. Design results in success to achieve real time encoder in quite compact size without losing flexibility and expand a bility. Real time emulation and easy test capability with external PC is al so implemented.