The online silicon vertex tracker (SVT) is composed of 104 VME 9U digital b
oards (of eight different types). Since the data output from the SVT (few M
B/s) are a small fraction of the input data (200 MB/s), it is extremely dif
ficult to track possible internal errors by using only the output stream. F
or this reason, several diagnostic tools have been implemented: local error
registers, error bits propagated through the data streams, and the Spy Buf
fer system. Data flowing through each input and output stream of every boar
d are continuously copied to memory banks named Spy Buffers, which act as b
uilt-in logic state analyzers hooked continuously to internal data streams.
The contents of all buffers can be frozen at any time (e.g., on error dete
ction) to take a snapshot of all data flowing through each SVT board. The S
py Buffers are coordinated at system level by the Spy Control Board. The ar
chitecture, design, and implementation of this system are described.