We describe a four-channel, digital-signal-processor-based readout board, e
quipped with analog-to-digital converters. A series of identical boards wor
k in parallel in the Belle experiment at KEK, performing a zero-suppressing
readout of the silicon vertex detector. A cluster-searching algorithm exec
utes quickly enough to allow low deadtime readout at a 500 Hz trigger rate.
DSP code downloaded to the boards can be easily modified, affording a high
degree of flexibility. We describe the board hardware, the algorithms empl
oyed in the experiment, and the software used to implement them. (C) 2001 E
lsevier Science B.V. All rights reserved.