Influence of high-level synthesis on average and peak temperatures of CMOScircuits

Citation
W. Szczesniak et al., Influence of high-level synthesis on average and peak temperatures of CMOScircuits, MICROELEC J, 32(10-11), 2001, pp. 855-862
Citations number
26
Language
INGLESE
art.tipo
Article
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
MICROELECTRONICS JOURNAL
ISSN journal
0026-2692 → ACNP
Volume
32
Issue
10-11
Year of publication
2001
Pages
855 - 862
Database
ISI
SICI code
0026-2692(200110/11)32:10-11<855:IOHSOA>2.0.ZU;2-F
Abstract
The aim of this paper is introducing a new modified high-level synthesis (H LS) technique resulting in reduction of the power dissipation in CMOS circu its leading to lowering the peak and the average temperature of the designe d chip. The presented approach enables us designing contemporary electronic systems with reduction of the peak and average power consumption, so the r eliability of the system can be improved. In the present method, the initia l HLS is performed by the ASAP algorithm [The Synthesis Approach to Digital System Design, 1992]. In the next stage, acceptable increase of the toggli ng time of chosen functional units (without exceeding the system throughput - the latency is constant) leads to the possibility of decreasing their su pply voltages. These chosen functional units are determined by the insertin g idle operations with interchanging (IIOI) algorithm. This approach leads to decreasing the power dissipated in the chosen functional units and final ly their peak and average temperature is lowered. (C) 2001 Elsevier Science Ltd. All rights reserved.