70 nm NMOSFET fabrication with 12 nm n(+)-p junctions using As-2(+) low energy implantations

Citation
By. Choi et al., 70 nm NMOSFET fabrication with 12 nm n(+)-p junctions using As-2(+) low energy implantations, JPN J A P 1, 40(4B), 2001, pp. 2607-2610
Citations number
7
Language
INGLESE
art.tipo
Article
Categorie Soggetti
Apllied Physucs/Condensed Matter/Materiales Science
Volume
40
Issue
4B
Year of publication
2001
Pages
2607 - 2610
Database
ISI
SICI code
0021-4922(200104)40:4B<2607:7NNFW1>2.0.ZU;2-O
Abstract
Nano-scale gate length metal oxide semiconductor field effect transistor (M OSFET) devices require extremely shallow source/drain extension regions wit h junction depth of 20-30 nm [The International Technology Roadmap for Semi conductors: Semiconductor Industry Association (1998)]. In this work, 12 nm n(+)-p junctions that are realized by using As-2(+) low energy (less than or equal to 10 keV) implantation show the low sheet resistance of 1.0k Omeg a/square after a rapid thermal annealing process. The As-2(+) implantation and RTA process make it possible to fabricate the nano-scale n-type metal o xide semiconductor field effect transistor (NMOSFET) with gate length of 70 nm, The As-2(+) 5 keV NMOSFET shows a small threshold voltage roll-off and a DIBL effect of 30 mV at 100 run gate length NMOSFET devices.