An area-effective datapath architecture for embedded microprocessors and scalable systems

Citation
T. Inoue et al., An area-effective datapath architecture for embedded microprocessors and scalable systems, IEICE TR EL, E84C(8), 2001, pp. 1014-1020
Citations number
8
Language
INGLESE
art.tipo
Article
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEICE TRANSACTIONS ON ELECTRONICS
ISSN journal
0916-8524 → ACNP
Volume
E84C
Issue
8
Year of publication
2001
Pages
1014 - 1020
Database
ISI
SICI code
0916-8524(200108)E84C:8<1014:AADAFE>2.0.ZU;2-0
Abstract
We have proposed area-reduction techniques for superscalar datapath archite ctures with 34 SIMD instructions and have developed an integer-media unit b ased on these techniques. The unit's design is both functionally asymmetric al and integer-SIMD unified, and the resulting savings in area are 27%-48% as compared to other, functionally equivalent mid-level microprocessor desi gns, with performance that is, at most, only 7.2%, lower. Further, in 2-D I DCT processing, the unit outperforms embedded microprocessor designs withou t SIMD functions by 49%-118%. Specifically, effective area reduction of add ers, shifters. and multiply-and-adders has been achieved by using the unifi ed design. These area-effective techniques are useful for embedded micropro cessors and scalable systems that employ highly parallel superscalar and on -chip parallel architectures. The integer-media unit has been implemented i n an evaluation chip fabricated with 0.15-mum 5-metal CMOS technology.