Architecture-level power estimation and design experiments

Citation
Ry. Chen et Mj. Irwin, Architecture-level power estimation and design experiments, ACM T DES A, 6(1), 2001, pp. 50-66
Citations number
13
Language
INGLESE
art.tipo
Article
Categorie Soggetti
Computer Science & Engineering
Journal title
ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS
ISSN journal
1084-4309 → ACNP
Volume
6
Issue
1
Year of publication
2001
Pages
50 - 66
Database
ISI
SICI code
1084-4309(200101)6:1<50:APEADE>2.0.ZU;2-A
Abstract
Architecture-level power estimation has received more attention recently be cause of its efficiency. This article presents a technique used to do power analysis of processors at the architecture level. It provides cycle-by-cyc le power consumption data of the architecture on the basis of the instructi on/data flow stream. To characterize the power dissipation of control units , a novel hierarchical method has been developed. Using this technique, a p ower estimator is implemented for a commercial processor. The accuracy of t he estimator is validated by comparing the power values it produces against measurements made by a gate-level power simulator for the same benchmark s et. Our estimation approach is shown to provide very efficient and accurate power analysis at the architecture level. The energy models built for firs t-pass estimation (such as ALU, MAC unit, register files) are reusable for future architecture design modification. In this article, we demonstrate th e application of the technique. Furthermore, this technique can evaluate va rious kinds of software to achieve hardware/software codesign for low power .