Steiner tree optimization for buffers, blockages, and bays

Citation
Cj. Alpert et al., Steiner tree optimization for buffers, blockages, and bays, IEEE COMP A, 20(4), 2001, pp. 556-562
Citations number
22
Language
INGLESE
art.tipo
Article
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
ISSN journal
0278-0070 → ACNP
Volume
20
Issue
4
Year of publication
2001
Pages
556 - 562
Database
ISI
SICI code
0278-0070(200104)20:4<556:STOFBB>2.0.ZU;2-M
Abstract
Timing optimization is a critical component of deep submicrometer design an d buffer insertion is an essential technique for achieving timing closure, This work studies buffer insertion under the constraint that the buffers ei ther: 1) avoid blockages or 2) are contained within preassigned buffer bay regions. We propose a general Steiner-tree formulation to drive this applic ation and present a maze-routing-based heuristic that either avoids blockag es or finds buffer bays. We show that the combination of our Steiner-tree o ptimization with leading-edge buffer-insertion techniques leads to effectiv e solutions on industry designs.