Application of dynamic pass-transistor logic to an 8-bit multiplier

Citation
Jd. Lee et al., Application of dynamic pass-transistor logic to an 8-bit multiplier, J KOR PHYS, 38(3), 2001, pp. 220-223
Citations number
5
Language
INGLESE
art.tipo
Article
Categorie Soggetti
Physics
Journal title
JOURNAL OF THE KOREAN PHYSICAL SOCIETY
ISSN journal
0374-4884 → ACNP
Volume
38
Issue
3
Year of publication
2001
Pages
220 - 223
Database
ISI
SICI code
0374-4884(200103)38:3<220:AODPLT>2.0.ZU;2-2
Abstract
Dynamic pass-transistor logic (PTL), which combines pass-transistor logic w ith dynamic logic, is proposed for high-performance VLSI circuit design. Th e dynamic PTL holds the merits of fast evaluation characteristics as dynami c logic. Moreover, because a pre-charged scheme solves the weak logic 'high ' problem of a static PTL, an additional level restoration circuit is not n eeded. An 8-bit multiplier is designed using dynamic PTL for the evaluation of its characteristics. The multiplier consists of a Booth's partial produ ct generator and a [4 : 2] compressor for a partial product reduction tree; For the comparison of performance, the multiplier is also designed using c onventional static CMOS logic. An HSPICE simulation is carried out with the 0.25 mum CMOS device model parameters used in Samsung Electronics Co. From the simulation, the delay of multiplier is 206.2 psec, and the power consu mption is 117.5 mW with a 3.3 V supply voltage, a 1 GHz operation and a 60 degreesC temperature. The results show that the multiplier designed by usin g dynamic PTL improves the speed by 2.5 times but consumes more power by 21 %; hence, the power delay product is improved by 50 % compared with a stat ic CMOS.