The state assignment of a finite state machine greatly affects the delay, a
rea and testability of sequential circuits. To reduce the length and number
of feedback cycles, a new state assignment technique based on m-block part
itioning is introduced. Following the completion of the proposed stare assi
gnment and logic synthesis stage, partial scan design is performed to choos
e the minimal number of scan flip-flops. Experimental results show that a d
rastic improvement in testability can be realised while maintaining a low a
rea and delay overhead.