Optimal state assignment technique for partial scan designs

Citation
S. Park et al., Optimal state assignment technique for partial scan designs, ELECTR LETT, 36(18), 2000, pp. 1527-1529
Citations number
4
Language
INGLESE
art.tipo
Article
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
ELECTRONICS LETTERS
ISSN journal
0013-5194 → ACNP
Volume
36
Issue
18
Year of publication
2000
Pages
1527 - 1529
Database
ISI
SICI code
0013-5194(20000831)36:18<1527:OSATFP>2.0.ZU;2-P
Abstract
The state assignment of a finite state machine greatly affects the delay, a rea and testability of sequential circuits. To reduce the length and number of feedback cycles, a new state assignment technique based on m-block part itioning is introduced. Following the completion of the proposed stare assi gnment and logic synthesis stage, partial scan design is performed to choos e the minimal number of scan flip-flops. Experimental results show that a d rastic improvement in testability can be realised while maintaining a low a rea and delay overhead.