A new FPGA architecture for high performance bit-serial pipeline datapath

Citation
A. Ohta et al., A new FPGA architecture for high performance bit-serial pipeline datapath, IEICE T FUN, E83A(8), 2000, pp. 1663-1672
Citations number
10
Language
INGLESE
art.tipo
Article
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES
ISSN journal
0916-8508 → ACNP
Volume
E83A
Issue
8
Year of publication
2000
Pages
1663 - 1672
Database
ISI
SICI code
0916-8508(200008)E83A:8<1663:ANFAFH>2.0.ZU;2-2
Abstract
In this paper, we present our work on the design of a new FPGA architecture targeted for high-performance bit-serial pipeline datapath. Bit-parallel s ystems require large amount of routing resource which is especially critica l in using FPGAs. Their device utilization and operation frequency become l ow because of large routing penalty. Whereas bit-serial circuits are very e fficient in routing, therefore are able to achieve a very high logic utiliz ation. Our proposed FPGA architecture is designed taking into account the s tructure of bit-serial circuits to optimize the logic and routing architect ure. Our FPGA guarantees near 100% logic utilization with a straightforward place and route tool due to high routability of bit-serial circuits and si mple routing interconnect architecture. The FPGA chip core which we designe d consists of around 200k transistors on 3.5 mm square substrate using 0.5 mu m a-metal CMOS process technology.