Novel capacitor process using diffusion barrier rounded by Si3N4 spacer for high density FRAM device

Citation
Bj. Koo et al., Novel capacitor process using diffusion barrier rounded by Si3N4 spacer for high density FRAM device, IEEE ELEC D, 21(6), 2000, pp. 280-282
Citations number
7
Language
INGLESE
art.tipo
Article
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEEE ELECTRON DEVICE LETTERS
ISSN journal
0741-3106 → ACNP
Volume
21
Issue
6
Year of publication
2000
Pages
280 - 282
Database
ISI
SICI code
0741-3106(200006)21:6<280:NCPUDB>2.0.ZU;2-1
Abstract
A novel capacitor process was successfully implemented in 4 Mb FRAM device by developing a barrier layer rounded by Si3N4 spacer (BRS) scheme. Using t his process, it is possible to eliminate an undesired barrier etching damag e, which is a major role in degrading ferroelectric properties, The novel c apacitor process was generated by etching an Ir barrier layer and rounding the barrier by Si3N4 spacer before preparing Pb(Zr1-xTix)O-3 (PZT) films. I t was observed that uniform sol-gel derived PZT films were prepared on the patterned Ir substrate by using Si3N4 spacer, which provides a smooth edge of the patterned cell. The contact resistance between bottom electrode and poly-silicon plug after full integration was monitored below 700 Ohm per co ntact with contact size 0.6 x 0.6 (mu m(2)). Compared to the ferroelectric capacitor damaged by barrier etching, the novel Pb(Zr1-xTix)O-3 (PZT) capac itor exhibited well-saturated Q-V curve. The fully processed novel capacito r having 1.2 x 1.2 (mu m(2)) effective area displayed remnant polarization of 14 (mu C/cm(2)) at an operating voltage of 3.0 V. The BRS ferroelectric capacitor showed a reliable retention property until 100 h at 125 degrees C . Same state retention (Qss) was stable with time up to 100 h while opposit e state retention (Qos) showed a log-linear decay rate at 125 degrees C the rmal stress.