A general level-specific lithography optimization methodology is applied to
the critical levels of a I-Gb DRAM design at 175- and 150-nm ground rules.
This three-step methodology-ruling oat inapplicable approaches by physical
principles, selecting promising techniques by simulation, and determining
actual process window by experimentation-is based on process latitude quant
ification using the total window metric. The optimal lithography strategy i
s pattern specific, depending on the illumination configuration, pattern sh
ape and size, mask technology, mask tone, and photoresist characteristics.
These large numbers of lithography possibilities are efficiently evaluated
by an accurate photoresist development bias model. Resolution enhancement t
echniques such as phase-shifting masks, annular illumination and optical pr
oximity correction are essential in enlarging the inadequate process latitu
de of conventional lithography.