Level-specific lithography optimization for 1-Gb DRAM

Citation
Ak. Wong et al., Level-specific lithography optimization for 1-Gb DRAM, IEEE SEMIC, 13(1), 2000, pp. 76-87
Citations number
51
Language
INGLESE
art.tipo
Article
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING
ISSN journal
0894-6507 → ACNP
Volume
13
Issue
1
Year of publication
2000
Pages
76 - 87
Database
ISI
SICI code
0894-6507(200002)13:1<76:LLOF1D>2.0.ZU;2-0
Abstract
A general level-specific lithography optimization methodology is applied to the critical levels of a I-Gb DRAM design at 175- and 150-nm ground rules. This three-step methodology-ruling oat inapplicable approaches by physical principles, selecting promising techniques by simulation, and determining actual process window by experimentation-is based on process latitude quant ification using the total window metric. The optimal lithography strategy i s pattern specific, depending on the illumination configuration, pattern sh ape and size, mask technology, mask tone, and photoresist characteristics. These large numbers of lithography possibilities are efficiently evaluated by an accurate photoresist development bias model. Resolution enhancement t echniques such as phase-shifting masks, annular illumination and optical pr oximity correction are essential in enlarging the inadequate process latitu de of conventional lithography.