Layout techniques to enhance the radiation tolerance of standard CMOS technologies demonstrated on a pixel detector readout chip

Citation
W. Snoeys et al., Layout techniques to enhance the radiation tolerance of standard CMOS technologies demonstrated on a pixel detector readout chip, NUCL INST A, 439(2-3), 2000, pp. 349-360
Citations number
21
Language
INGLESE
art.tipo
Article
Categorie Soggetti
Spectroscopy /Instrumentation/Analytical Sciences","Instrumentation & Measurement
Journal title
NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH SECTION A-ACCELERATORS SPECTROMETERS DETECTORS AND ASSOCIATED EQUIPMENT
ISSN journal
0168-9002 → ACNP
Volume
439
Issue
2-3
Year of publication
2000
Pages
349 - 360
Database
ISI
SICI code
0168-9002(20000111)439:2-3<349:LTTETR>2.0.ZU;2-A
Abstract
A new pixel readout prototype has been developed at CERN for high-energy ph ysics applications. This full mixed mode circuit has been implemented in a commercial 0.5 mu m CMOS technology. Its radiation tolerance has been enhan ced by designing all NMOS transistors in enclosed geometry and introducing guardrings wherever necessary. The technique is explained and its effective ness demonstrated on various irradiation measurements on individual transis tors and on the prototype. Circuit performance started to degrade only afte r a total dose of 600 krad-1.7 Mrad depending on the type of radiation. 10 keV X-rays, Co-60 gamma-rays, 6.5 MeV protons, and minimum ionizing particl es were used. implications of this layout approach on the circuit design an d perspectives for even deeper submicron technologies are discussed. (C) 20 00 Elsevier Science B.V. All rights reserved.