A 256-Mb flash memory is fabricated with a 0.25-mu m AND-type memory cell a
nd 2-bit/cell multilevel technique on a 138.6-mm(2) die. Parallel decoding
of four memory threshold voltage levels to 2-bit logical values prevents th
roughput degradation due to multilevel operation. This parallel decoding ha
s been achieved by sense latches and data latches connected to each bitline
, Tight distribution of memory cell threshold voltage is essential to relia
ble multilevel operation, This chip has several measures to deal with the f
actors that widen the memory cell V-th. The effect of adjacent memory cell'
s V-th is eliminated by using an AND-type flash memory cell. Initial distri
bution width of 0.1 V is achieved. Wordline voltage, which has negative tem
perature dependency, compensates the positive dependency of memory cell V-t
h. In the -5-75 degrees C range, memory threshold V-th deviation is reduced
from the conventional 0.19-0.07 V, Conventionally, the number of programs
without erase operation per one sector is limited by the limitations from p
rogram disturb. This chip introduced a new rewrite scheme, and this limit i
s increased from the conventional 10-2048 + 64 times/sector.