A low-power, sparse-scan, readout architecture has been-developed for the A
TLAS pixel front-end electronics. The architecture supports a dual discrimi
nator and extracts the time over threshold (TOT) information along with a 2
-D spatial address of the hits and associates them with a unique 7-bit beam
crossing number. The IC implements level-1 trigger filtering along with ev
ent building (grouping together all hits in a beam crossing) in the end of
column (EOC) buffer. The events are transmitted over a 40 MHz serial data l
ink with the protocol Supporting buffer overflow handling by appending erro
r flags td events.
This mixed-mode full custom IC is implemented in 0.8 mu HP process to meet
the requirements for the pixel readout in the ATLAS inner detector. The cir
cuits have been tested and the IC has been found to provide deadtime-less a
mbiguity-free readout at 40MHz data rate.