Results: 1-4 |
Results: 4

Authors: Inoue, T Manabe, T Torii, S Matsushita, S Edahiro, M Nishi, N Yamashina, M
Citation: T. Inoue et al., An area-effective datapath architecture for embedded microprocessors and scalable systems, IEICE TR EL, E84C(8), 2001, pp. 1014-1020

Authors: Takahashi, S Edahiro, M Hayashi, Y
Citation: S. Takahashi et al., Interconnect design strategy: Structures, repeaters and materials with strategic system performance analysis (S(2)PAL) model, IEEE DEVICE, 48(2), 2001, pp. 239-251

Authors: Edahiro, M Matsushita, S Yamashina, M Nishi, N
Citation: M. Edahiro et al., A single-chip multiprocessor for smart terminals, IEEE MICRO, 20(4), 2000, pp. 12-20

Authors: Kobayashi, S Edahiro, M Kubo, M
Citation: S. Kobayashi et al., A VLSI scan-chain optimization algorithm for multiple scan-paths, IEICE T FUN, E82A(11), 1999, pp. 2499-2504
Risultati: 1-4 |