Results: 1-19 |

Table of contents of journal: *IIE transactions

Results: 19

Authors: Kogan, K Khmelnitsky, E Levner, E
Citation: K. Kogan et al., A combinatorial approach to a class of parallel-machine, continuous-time scheduling problems, IIE TRANS, 34(3), 2002, pp. 223-231

Authors: Elhafsi, M
Citation: M. Elhafsi, Optimal leadtimes planning in serial production systems with earliness andtardiness costs, IIE TRANS, 34(3), 2002, pp. 233-243

Authors: Bukchin, J Luquer, R Shtub, A
Citation: J. Bukchin et al., Learning in tele-operations, IIE TRANS, 34(3), 2002, pp. 245-252

Authors: Zheng, SH
Citation: Sh. Zheng, Dynamic release policies for software systems with a reliability constraint, IIE TRANS, 34(3), 2002, pp. 253-262

Authors: Miltenburg, J Cheng, CH Yan, HM
Citation: J. Miltenburg et al., Analysis of wafer fabrication facilities using four variations of the openqueueing network decomposition model, IIE TRANS, 34(3), 2002, pp. 263-272

Authors: Laguna, M Marti, R
Citation: M. Laguna et R. Marti, Neural network prediction in a system for optimizing simulations, IIE TRANS, 34(3), 2002, pp. 273-282

Authors: Rees, LP Greenwood, AG Siochi, FC
Citation: Lp. Rees et al., A best-first search approach for determining starting regions in simulation optimization, IIE TRANS, 34(3), 2002, pp. 283-295

Authors: Cario, MC Clifford, JJ Hill, RR Yang, JW Yang, KJ Reilly, CH
Citation: Mc. Cario et al., An investigation of the relationship between problem characteristics and algorithm performance: a case study of the GAP, IIE TRANS, 34(3), 2002, pp. 297-312

Authors: Ramirez-Beltran, ND Montes, JA
Citation: Nd. Ramirez-beltran et Ja. Montes, Neural networks to model dynamic systems with time delays, IIE TRANS, 34(3), 2002, pp. 313-327

Authors: Curry, GL Deuermeyer, BL
Citation: Gl. Curry et Bl. Deuermeyer, Renewal approximations for the departure processes of batch systems, IIE TRANS, 34(2), 2002, pp. 95-104

Authors: Chung, SH Huang, HW
Citation: Sh. Chung et Hw. Huang, Cycle time estimation for wafer fab with engineering lots, IIE TRANS, 34(2), 2002, pp. 105-118

Authors: Hopp, WJ Spearman, ML Chayet, S Donohue, KL Gel, ES
Citation: Wj. Hopp et al., Using an optimized queueing network model to support wafer fab design, IIE TRANS, 34(2), 2002, pp. 119-130

Authors: Christie, RME Wu, SD
Citation: Rme. Christie et Sd. Wu, Semiconductor capacity planning: stochastic modelingand computational studies, IIE TRANS, 34(2), 2002, pp. 131-143

Authors: Swaminathan, JM
Citation: Jm. Swaminathan, Tool procurement planning for wafer fabrication facilities: a scenario-based approach, IIE TRANS, 34(2), 2002, pp. 145-155

Authors: Hung, YF Cheng, GJ
Citation: Yf. Hung et Gj. Cheng, Hybrid capacity modeling for alternative machine types in linear programming production planning, IIE TRANS, 34(2), 2002, pp. 157-165

Authors: Kim, S Yea, SH Kim, B
Citation: S. Kim et al., Shift scheduling for steppers in the semiconductor wafer fabrication process, IIE TRANS, 34(2), 2002, pp. 167-177

Authors: Lee, YH Park, J Kim, S
Citation: Yh. Lee et al., Experimental study on input and bottleneck scheduling for a semiconductor fabrication line, IIE TRANS, 34(2), 2002, pp. 179-190

Authors: Sloan, TW Shanthikumar, JG
Citation: Tw. Sloan et Jg. Shanthikumar, Using in-line equipment condition and yield information for maintenance scheduling and dispatching in semiconductor wafer fabs, IIE TRANS, 34(2), 2002, pp. 191-209

Authors: Pearn, WL Chung, SH Yang, MH
Citation: Wl. Pearn et al., Minimizing the total machine workload for the wafer probing scheduling problem, IIE TRANS, 34(2), 2002, pp. 211-220
Risultati: 1-19 |