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Table of contents of journal: *IEICE transactions on electronics

Results: 1-25/1533

Authors: MURAKAMI K
Citation: K. Murakami, SPECIAL ISSUE ON NOVEL VLSI PROCESSOR ARCHITECTURES, IEICE transactions on electronics, E81C(9), 1998, pp. 1373-1373

Authors: SATO H YOSHIDA T MATSUO M KENGAKU T TSUCHIHASHI K
Citation: H. Sato et al., A DUAL-ISSUE RISC PROCESSOR FOR MULTIMEDIA SIGNAL-PROCESSING, IEICE transactions on electronics, E81C(9), 1998, pp. 1374-1381

Authors: YAMADA A YOSHIDA T MATSUMURA T URAMOTO S TSUCHIHASHI K HOLMANN E
Citation: A. Yamada et al., A REAL-TIME MPEG2 ENCODING AND DECODING ARCHITECTURE WITH A DUAL-ISSUE RISC PROCESSOR, IEICE transactions on electronics, E81C(9), 1998, pp. 1382-1390

Authors: MATSUOKA H OKAMOTO K HIRONO H SATO M YOKOTA T SAKAI S
Citation: H. Matsuoka et al., PROCESSOR PIPELINE DESIGN FOR PAST NETWORK MESSAGE HANDLING IN RWC-1 MULTIPROCESSOR, IEICE transactions on electronics, E81C(9), 1998, pp. 1391-1397

Authors: SATO T
Citation: T. Sato, A MICROPROCESSOR ARCHITECTURE UTILIZING HISTORIES OF DYNAMIC SEQUENCES SAVED IN DISTRIBUTED MEMORIES, IEICE transactions on electronics, E81C(9), 1998, pp. 1398-1407

Authors: INAMORI M ISHII K TSUTSUI A SHIRAKAWA K MIYAZAKI T NAKADA H
Citation: M. Inamori et al., A NEW PROCESSOR ARCHITECTURE FOR DIGITAL SIGNAL TRANSPORT-SYSTEMS, IEICE transactions on electronics, E81C(9), 1998, pp. 1408-1415

Authors: NURPRASETYO EF INOUE A TOMIYAMA H YASUURA H
Citation: Ef. Nurprasetyo et al., SOFT-CORE PROCESSOR ARCHITECTURE FOR EMBEDDED SYSTEM-DESIGN, IEICE transactions on electronics, E81C(9), 1998, pp. 1416-1423

Authors: TAN BK OGAWA T YOSHIMURA R TANIGUCHI K
Citation: Bk. Tan et al., A RECONFIGURABLE DIGITAL SIGNAL PROCESSOR, IEICE transactions on electronics, E81C(9), 1998, pp. 1424-1430

Authors: NAGAMI K OGURI K SHIOZAWA T ITO H KONISHI R
Citation: K. Nagami et al., PLASTIC CELL ARCHITECTURE - A SCALABLE DEVICE ARCHITECTURE FOR GENERAL-PURPOSE RECONFIGURABLE COMPUTING, IEICE transactions on electronics, E81C(9), 1998, pp. 1431-1437

Authors: INOUE K KAI K MURAKAMI K
Citation: K. Inoue et al., HIGH-BANDWIDTH, VARIABLE LINE-SIZE CACHE ARCHITECTURE FOR MERGED DRAMLOGIC LSIS/, IEICE transactions on electronics, E81C(9), 1998, pp. 1438-1447

Authors: KAI K INOUE A OHSAWA T MURAKAMI K
Citation: K. Kai et al., ANALYZING AND REDUCING THE IMPACT OF SHORTER DATA RETENTION TIME ON THE PERFORMANCE OF MERGED DRAM LOGIC LSIS/, IEICE transactions on electronics, E81C(9), 1998, pp. 1448-1454

Authors: OHSAWA T KAI K MURAKAMI K
Citation: T. Ohsawa et al., EVALUATING DRAM REFRESH ARCHITECTURES FOR MERGED DRAM LOGIC LSIS/, IEICE transactions on electronics, E81C(9), 1998, pp. 1455-1462

Authors: MIZUNO M ABIKO H FURUTA K SAKAI I YAMASHINA M
Citation: M. Mizuno et al., DEVICE-DEVIATION TOLERANT ELASTIC-VT CMOS CIRCUITS WITH FINE-GRAIN POWER-CONTROL CAPABILITY, IEICE transactions on electronics, E81C(9), 1998, pp. 1463-1472

Authors: ISHIHARA T YASUURA H
Citation: T. Ishihara et H. Yasuura, PROGRAMMABLE POWER MANAGEMENT ARCHITECTURE FOR POWER REDUCTION, IEICE transactions on electronics, E81C(9), 1998, pp. 1473-1480

Authors: FURUICHI S AIHARA T
Citation: S. Furuichi et T. Aihara, ADAPTIVE SPEED CONTROL OF A GENERAL-PURPOSE PROCESSOR BASED ON ACTIVITIES, IEICE transactions on electronics, E81C(9), 1998, pp. 1481-1483

Authors: NAKASE Y MASHIKO K MATSUDA Y TOKUDA T
Citation: Y. Nakase et al., A 300 MHZ DUAL-PORT PALETTE RAM USING PORT SWAP ARCHITECTURE, IEICE transactions on electronics, E81C(9), 1998, pp. 1484-1490

Authors: ENDOH T SHINMEI K SAKURABA H MASUOKA F
Citation: T. Endoh et al., THE ANALYSIS OF THE STACKED SURROUNDING GATE TRANSISTOR (S-SGT) DRAM FOR THE HIGH-SPEED AND LOW-VOLTAGE OPERATION, IEICE transactions on electronics, E81C(9), 1998, pp. 1491-1498

Authors: MAEDA Y YAMADA T
Citation: Y. Maeda et T. Yamada, OPTICAL SIGNAL INVERSION PHENOMENON DERIVED FROM THE NEGATIVE NONLINEAR ABSORPTION EFFECT IN ER3+LIYF4, IEICE transactions on electronics, E81C(9), 1998, pp. 1499-1504

Authors: KODAMA M UESUGI T
Citation: M. Kodama et T. Uesugi, TEMPERATURE CHARACTERISTICS OF LATERAL POWER MOS FET FORMED BY SOLID-PHASE EPITAXY, IEICE transactions on electronics, E81C(9), 1998, pp. 1505-1507

Authors: SUZAKI Y SEKINE S SUZUKI Y TOBA H
Citation: Y. Suzaki et al., A 1.3-MU-M OPTICAL TRANSCEIVER DIODE MODULE USING PASSIVE ALIGNMENT TECHNIQUE ON A SI BENCH WITH A V-GROOVE, IEICE transactions on electronics, E81C(9), 1998, pp. 1508-1510

Authors: YOSHIKUNI Y EMURA K
Citation: Y. Yoshikuni et K. Emura, SPECIAL ISSUE ON HIGH-CAPACITY WDM TDM NETWORKS - OPTICAL-DEVICES ANDTHEIR SYSTEM APPLICATIONS/, IEICE transactions on electronics, E81C(8), 1998, pp. 1157-1158

Authors: WAGNER RE
Citation: Re. Wagner, REALIZING THE VISION OF MULTIWAVELENGTH OPTICAL NETWORKING, IEICE transactions on electronics, E81C(8), 1998, pp. 1159-1166

Authors: OGUCHI K NAGATSU N
Citation: K. Oguchi et N. Nagatsu, STANDARDIZATION ACTIVITIES FOR OPTICAL NETWORKING RELEVANT ISSUES, IEICE transactions on electronics, E81C(8), 1998, pp. 1167-1175

Authors: OKAMOTO K INOUE Y TANAKA T OHMORI Y
Citation: K. Okamoto et al., SILICA-BASED PLANAR LIGHTWAVE CIRCUITS FOR WDM APPLICATIONS, IEICE transactions on electronics, E81C(8), 1998, pp. 1176-1186

Authors: KOKUBUN Y YONEDA S MATSUURA S
Citation: Y. Kokubun et al., ATHERMAL NARROW-BAND OPTICAL FILTER AT 1.55 MU-M WAVELENGTH BY SILICA-BASED ATHERMAL WAVE-GUIDE, IEICE transactions on electronics, E81C(8), 1998, pp. 1187-1194
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